There is a constant need to shrink the size of electrically programmable and erasable nonvolatile memory cells. However, as memory cell sizes scale down, dimension size changes result in changes in capacitive coupling between memory cell elements, and in the widths of various critical regions, all of which have the potential to negatively affect the operation margin of the memory cells, unless significant design changes are made to the structure of the memory cell. Further, as floating gate sizes scale down, an erased floating gate has decreased capacity for storing positive charges, which leads to lower signal-to-noise (SNR) ratios and higher error rates unless design changes are made to compensate.